As is known, memories are comprised of memory arrays made up of a plurality of cells arranged in rows and columns.
Generally, the rows are referred to as "word lines", whilst the columns are referred to as "bit lines".
In the design of a memory of the Flash EEPROM type, which uses CMOS technology, it is necessary to take into consideration the aspects linked to the use of processes of fabrication that are not yet completely stabilized and, in certain cases, are even still undergoing study.
One of the most frequent problems arising from the use of these processes is that of the formation of short circuits between two or more adjacent word lines/bit lines.
More in particular, FIG. 1 shows a memory device 1 comprising a memory array 2 made up of cells 3, only some of which are shown in this figure.
Each memory cell 3 comprises a floating gate transistor having drain and source conduction terminals.
The cells 3 are arranged in a plurality of local word lines, designated by LWL0, LWL1, LWL2, LWL3, which are physically made up of strips of polysilicon (poly2), with all the gate terminals of the cells of any given word line being connected together.
In turn, each bit line, made by means of metallic conductive paths (metal 1), connects up together the drain terminals of the cells arranged in one and the same column, whilst the source terminals are connected to a source line common to all the cells.
Alongside a packet of local word lines there is provided a global word line MWL0 connected to an output node of a voltage regulator REG, which generates as output a regulated voltage Vr, and to a first decoder 18 of global word lines.
In FIG. 1, the memory device 1 uses a second decoder for addressing the local word lines LWL0, LWL1, LWL2, LWL3.
The second decoder is schematically represented by a plurality of inverters 4, one for each local word line LWL0, LWL1, LWL2, LWL3, each inverter being driven by an end decoder 5 and comprising a PMOS transistor M' which has its conduction terminals connected between a local word line, for example LWL0, and the global word line MWL0, and an NMOS transistor M" which has its conduction terminals connected between the local word line LWL0 and a ground terminal GND.
The inverters 4 are driven so that they activate, from among the transistors M', only the one corresponding to the local word line that it is intended to address (word line selected), whereas all the remaining local word lines are connected to ground by the turning on of the respective transistors M".
With the reduction of the pitch between adjacent word lines/bit lines due both to the reduction in the size of memory devices and to the evolution of the processes for their integration, there is an increasing likelihood of these lines coming into contact with each other, thus generating short circuits.
To overcome this problem, generally the so called "redundancy method" is used, which consists in providing extra bit lines/word lines for replacing any bit lines/word lines that may get damaged.
FIG. 2, in which each word line is represented by a distributed RC network, shows a few examples of short circuits that may occur between adjacent word lines.
More in particular, one first type of short circuit (non resistive) occurs when the inverters 4.1 and 4.2 (or 4.3 and 4.4) for two short circuited word lines LWL1 and LWL2 (or LWL3 and LWL4) are connected directly, as represented in FIG. 2 by the dashed line CORT1.
A second type of short circuit (resistive) occurs when an inverter 4.5 for a word line LWL5 is connected to the end of another word line LWL1, as represented in FIG. 2 by the dashed line CORT2. In this case, between the inverter 4.5 and ground a resistance Rw is present.
A third type of short circuit (resistive) occurs when the ends of two word lines LWL1 and LWL2 (or LWL3 and LWL4) are short circuited, as represented in FIG. 2 by the dashed line CORT3. In this case, between the inverter (for example 4.1 or 4.3) connected to the selected word line and ground a resistance 2Rw is present.
Currently, the check on the integrity of word lines is carried out in the stage of testing of the memory device and consists in performing a sophisticated algorithm which is implemented externally and is based upon a cross check on appropriate configurations of data written inside the cells 3.
The use of the above mentioned algorithm entails an increase both in the times and in the costs involved in the testing stage, in that it means that, in order to check the data configurations, it is necessary for the cells 3 to be first written, then read, and finally erased, once the presence or otherwise of short circuits has been verified.
Consequently, this known solution is complex, costly and involves a considerable amount of time.